1. Field of the Invention
This invention relates to integrated circuit technology in general, and more particularly, to circuits that generate reference voltage in said technology.
2. Prior Art
Rapid improvements in the development of integrated circuit technology have made it possible to combine analog and digital circuits on the same chip. In the past, separate integrated circuit modules were used to package analog and digital circuits, respectively. With separate packaging, one would select a process that optimizes the fabrication of a particular circuit type. However, by combining the two types of circuits on a single chip, it is desirable to select a process that at least optimizes the fabrication of the circuits that dominate the chip.
In addition, each type of circuit usually requires unique functions that may not be needed by the other type of circuit. Thus, it is desirable to use a process that optimizes the implementation of these functions.
It has been determined that a "digital CMOS process" is effective in implementing mixed circuit (i.e., digital and analog) integrated chips. Usually, the analog circuits in CMOS are a small part of a predominantly digital circuit chip. Thus, the "digital CMOS process" optimizes the implementation of devices that are needed to implement the digital portion of the chip. Devices that are needed to implement analog functions are not available. Thus, a circuit designer is faced with the awesome task of using digitally friendly devices to implement analog functions. Among the many analog functions which a designer must provide is a stable reference voltage.
The generation of a reference voltage using CMOS technology has been done in the past. Known prior art implementation uses two FETs with different threshold voltages. The differential voltage resulting from the different thresholds is the reference voltage. The prior art also teaches that the device threshold voltages can be controlled by ion implantation and different device geometrics. Examples of the prior art teachings are set forth in U.S. Pat. Nos. 4,442,398; 4,305,011; 4,464,588; 4,100,437; 4,327,320; 4,472,871 and 4,453,094.
Other publications addressing CMOS reference voltage generators are:
1. Gray, P.R. and Meyer, R.G., "Analysis and Design of Analog Integrated Circuits," 2nd edition, Wiley, New York, 1983, Chapter 12.
2. Blauschild, R.A., et al, "A New NMOS Temperature-Stable Voltage Reference," IEEE JSSC, December 1978, pp. 767-773.
3. Song, B.S. and Gray, P.R., "A Precision Curvature-Connected CMOS Bandgap Reference," Digest of Papers, 1983, ISSCC.
4. Liu, S., and Nagel, L.W., "Small-Signal MOSFET Models for Analog Circuit Design," IEEE JSSC, December 1982, pp. 983-998.
5. Gregorian, R. et al, "Switched-Capacitor Circuit Design," IEEE Proceedings, August 1983, pp. 941-966.
A common problem faced by these designs is that there is a wide variation in the range of threshold voltages. It is believed that the wide variation in theshold voltages is caused by variation in the process used to fabricate the chip. Another common problem is that non-CMOS structures such as bipolar structures are fabricated in the LSI chip. This requires additional process steps which increase the cost of the chip.